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Introduction
This core is a simple and fast I/O controller with FSL master/slave
interface for Xilinx Microblaze softcore processor.
It should be faster and save more slices than any OBP version.
Basic software drivers included
Features write, set mask, clear mask and toggle mask write operations
Features Write while Read operations
Features input rising/falling edge triggered clear output operations
Xilinx EDK 6.3 required
Tested on Spartan3 MB1500 evaluation board (not all functions
are fully tested)
Any feedback will be appreciated
I/O port
FSL_S_* : Slave FSL connection
FSL_M_* : Master FSL connection
inputs : generic input lines
outputs : generic output lines
cmd_end : special input lines for edge triggered clear output
Configuration parameters
FSL_DATA_BITS (16) : FSL data width
OUTPUT_BITS (8) : Number of outputs
INPUT_BITS (8) : Number of inputs
START_BITS (0) : Number of input/outputs dedicated to edge triggered
clear
START_CMD_RISING (0): Select falling edge (0) or rising edge (1)
for edge triggered clear
Software API
Write Operations
void Xfsl_IOctrl_WriteOutputs( Xuint32 Value ); Write a value
to all the output lines
void Xfsl_IOctrl_SetOutputs( Xuint32 Mask); Set (->1) output
lines indicated by Mask
void Xfsl_IOctrl_ClearOutputs( Xuint32 Mask); Clear (->0)
output lines indicated by Mask
void Xfsl_IOctrl_ToggleOutputs( Xuint32 Mask); Toggle (0->1,
1->0) output lines indicated by Mask
Read Operations
Xuint32 Xfsl_IOctrl_ReadInputs( void); Read Input lines
Xuint32 Xfsl_IOctrl_ReadOutputs( void); Read back Output lines
Read + Write Operations
Xuint32 Xfsl_IOctrl_ReadInputsWriteOutputs( Xuint32 Value
); Read Input lines while Write output lines
Xuint32 Xfsl_IOctrl_ReadInputsToggleOutputs( Xuint32 Mask
); Read Input lines while Toggle output lines
## Example of use in MSH file (12 outputs and 8 inputs)
PORT fsl_ioctrl_0_inputs = fsl_ioctrl_0_inputs, VEC = [7:0], DIR = IN
PORT fsl_ioctrl_0_outputs = fsl_ioctrl_0_outputs, VEC = [11:0], DIR = OUT
BEGIN fsl_ioctrl
PARAMETER INSTANCE = fsl_ioctrl_0
PARAMETER HW_VER = 1.01.b
PARAMETER OUTPUT_BITS = 12
PARAMETER INPUT_BITS = 8
BUS_INTERFACE MFSL = fsl_v20_1
BUS_INTERFACE SFSL = fsl_v20_2
PORT clk = sys_clk_s
PORT inputs = fsl_ioctrl_0_inputs
PORT outputs = fsl_ioctrl_0_outputs
END
BEGIN fsl_v20
PARAMETER INSTANCE = fsl_v20_1
PARAMETER HW_VER = 2.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PARAMETER C_FSL_DWIDTH = 16
PARAMETER C_FSL_DEPTH = 1
PORT FSL_Clk = sys_clk_s
PORT SYS_Rst = sys_rst_s
END
BEGIN fsl_v20
PARAMETER INSTANCE = fsl_v20_2
PARAMETER HW_VER = 2.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PARAMETER C_FSL_DWIDTH = 16
PARAMETER C_FSL_DEPTH = 1
PORT FSL_Clk = sys_clk_s
PORT SYS_Rst = sys_rst_s
END
##########################
Example of use in MSS file
BEGIN DRIVER
PARAMETER DRIVER_NAME = fsl_ioctrl
PARAMETER DRIVER_VER = 1.01.b
PARAMETER HW_INSTANCE = fsl_ioctrl_0
END
######################################
Simple example of use in C source file
#include "fsl_ioctrl.h"
void fsl_io_test(void)
{
int k, j;
unsigned int in_val;
for (j = 0; j < 12; j++)
{
Xfsl_IOctrl_WriteOutputs( (1 << j) );
in_val = Xfsl_IOctrl_ReadOutputs();
if ( in_val != (1 << j) )
xil_printf("Read back Outputs error, %x differ from %x\r\n", (1 << j), in_val);
for (k = 0; k < 100000; k++)
;;; //wait
}
in_val = Xfsl_IOctrl_ReadInputs();
xil_printf("Data read from Input: 0x%02X\r\n", in_val);
}
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fsl_ioctrl.zip